This invention is generally directed to time division multiplexers and more specifically to hardware based implementations of same.
Hardware based time division multiplexers can be implemented by custom LSI integrated circuits (IC's) and by discrete logic elements. The LSI integrated circuit offers an efficient method of implementing a time division multiplexer but is relatively costly. Also, any enhancements of the basic multiplexer design after fabrication of the custom IC requires another design and another LSI IC.
Implementation of a multiplexer by discrete logic integrated circuits is relatively inexpensive and offers a design which can be easily modified. However, conventional discrete logic implementations suffer from the disadvantage that the amount of integrated circuits required increases substantially when a large range of data rates are required or a large number of channels is needed.
Discrete logic multiplexer approaches may use two shift registers: one to store channel data at a channel clock rate and the other to clock out channel data to the multiplex channel at the baseband rate. Normally, serial-out, parallel-in shift registers are used so that channel data can be quickly loaded from one register to the other via parallel transfer and serially clocked out of the loaded register to the multiplex channel. Such shift resgisters are available in six, seven, and eight bit lengths. Thus, when there is a need for more than eight bits multiple shift registers must be used.